Junior/ Senior Digital Design Engineer

Credo · Hong Kong

Job Description

Duties • Microarchitecture and design in Verilog/System Verilog. • Define and own ASIC design methodologies. • Integrate complex IPs developed by internal groups as well other vendors. • Block and Chip level RTL verification and gate-level netlist testing. • Support other ASIC design activities such as Lint, CDC checks, formal verification,synthesis, and DFT. • Support back-end engineers with timing-closure and ECOs. • Chip bring up, validation and debug. • Support Firmware development and Applications teams.

Credo

Hong Kong

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Junior/ Senior Digital Design Engineer

Job Description

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